SigmaQuad SRAMs are synchronous memories with separate read and write data buses. “Quad” refers to their ability to transfer 4 beats of data (2 beats per data bus) in a single clock cycle.
SigmaDDR SRAMs are synchronous memories with a common read and write data bus. “DDR” refers to their ability to transfer 2 beats of data on the data bus in a single clock cycle. GSI’s SigmaQuad and SigmaDDR devices are compatible with all competitor Quad Data Rate and Double Data Rate SRAMs, respectively.
• 1.1G memory transactions per second (SigmaQuad-II+™) • Extensive range of design options—Quad & Double Data Rates, 1.5–2.5 cycle Read Latencies, 2- and 4-word data bursts • User-configurable signal termination and output drive settings • Densities for every performance point—18Mbit up to 288Mbit • Constructed using foundry-standard CMOS and 165-bump BGA packaging (both leaded and RoHS-compliant options)